Introduction
This is a top-level index page, covering my first foray into FPGA programming. All of the experiments use the IceStorm toolchain running on a Mac to program iCE40 FPGAs from Lattice.
The articles exist both to clarify things in my own mind now, and because I think my future self might find explicit instructions for making an LED blinky useful. Who knows, maybe other people will too!
I should say that although the verilog presented here appears to work, these are my first verilog programs, and so are doubtless far from model code.
One article covers the toolchain1, which covers both installing and invoking things
Others cover different development boards: the IceStick2 and HX8K Breakout3 boards from Lattice; a HX1K4 board from Olimex.
Were I starting afresh now, I’d stick to the HX8K board from Lattice. It boasts a significantly more capable FPGA, can be programmed more quickly, and sits nicely on the desk.
Verilog Resources
This is just a random sample of interesting articles which seemed good to me, but I put large error-bars on that judgement.
Introductory articles
- A verilog tutorial5, though a lot of the early stuff isn’t relevant for synthesis6.
- Gisselquist Technology7 has a list of Rules for new FPGA designers8.
- Embedded Micro’s9 page of tutorials10.
Specific designs
- OpenCores11 a smörgåsbord of open designs.
- Pseudorandom numbers12 at Gisselquist.
- FIFOs13 at Gisselquist.
- Buttons14 at Gisselquist.
- PWM15 at Gisselquist.
- Pointers to UARTs16.
Philosophical articles
- At Gisselquist17, and a newer post about formal methods18.
Wishbone Bus
The Wishbone Bus19 is a standard for connecting different parts of design to each other.
It seems common at OpenCores.
Gisselquist have loads of good articles about it, including:
- A Wishbone-UART bridge20 to connect the host computer to the bus.
- A Wishbone scope21 which lets you watch the design’s behaviour from within (tutorial22).
- A Wishbone slave23.
Clifford Wolf’s PicoRV RISC-V CPU24 has a Wishbone version.
References
- 1. ./ice40-toolchain.html
- 2. ./ice40-blinky-icestick.html
- 3. ./ice40-blinky-hx8k-breakout.html
- 4. ./ice40-blinky-olimex-hx1k.html
- 5. http://www.asic-world.com/verilog/veritut.html
- 6. http://www.asic-world.com/verilog/synthesis.html
- 7. http://zipcpu.com
- 8. http://zipcpu.com/blog/2017/08/21/rules-for-newbies.html
- 9. https://embeddedmicro.com/
- 10. https://embeddedmicro.com/pages/verilog
- 11. https://opencores.org
- 12. http://zipcpu.com/dsp/2017/10/27/lfsr.html
- 13. http://zipcpu.com/blog/2017/07/29/fifo.html
- 14. http://zipcpu.com/blog/2017/08/04/debouncing.html
- 15. http://zipcpu.com/dsp/2017/09/04/pwm-reinvention.html
- 16. https://github.com/cliffordwolf/icestorm/issues/51
- 17. http://zipcpu.com/blog/2017/06/23/my-dbg-philosophy.html
- 18. http://zipcpu.com/blog/2017/10/19/formal-intro.html
- 19. https://en.wikipedia.org/wiki/Wishbone_(computer_bus)
- 20. http://zipcpu.com/blog/2017/06/05/wb-bridge-overview.html
- 21. https://github.com/ZipCPU/wbscope
- 22. http://zipcpu.com/blog/2017/07/08/getting-started-with-wbscope.html
- 23. http://zipcpu.com/zipcpu/2017/05/29/simple-wishbone.html
- 24. https://github.com/cliffordwolf/picorv32